Killivalavan Chitravel
RTL Design Engineer
- Role
- Intern at Edgeq Inc
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
About Killivalavan Chitravel
I\'m an electrical engineering graduate student at USC, specializing in Digital VLSI and Computer Architecture. I have 6 years of professional experience as RTL Design Engineer and have designed modules for SOC peripherals and LTE Uplink Physical Layers. I am interested in Digital Design, Design Verification and Physical Design roles.
Experience
Intern
Jun 2023 — Present · US
Education
USC Viterbi School of Engineering
Master's degree
2022 — 2023
Sri Manakula Vinayagar Engineering College
Bachelor's degree
2011 — 2015
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