Khayer Mohammad

About Khayer Mohammad

I am currently working as a Foundry Product Development Engineering Manager at Intel Corporation where I lead and manage a team of engineers to deliver for Intel\'s test technology product testing. I started up and integrated this team from ground up starting from hiring the engineers, training, mentoring them, and ramping up the engineers with the required skillsets, and integrating them into a coherent team focused to deliver the software and test capability enablement for Intel’s product test technology development. Our work involves problem solving based on next generation product test requirements and demand, planning, brainstorming, developing, validating software and hardware co-design, collaborate and work closely with internal and external customers and vendors to develop, debug, validate, and release software and hardware stack to production that meet the demand for Intel’s next generation high-power and high-volume product testing. We develop machine learning (ML) and artificial intelligence (AI) based software package to drive the hardware stack in a high-volume automated test environment to deliver efficient and enhanced test capabilities such as thermals, power management with reduced cost. We support the high-volume product test throughout the product life cycles until the product certification and shipping to customers.Lead Engineer with 10+ years of hands-on experience in the area of product/test vehicle test, characterization, validation and high-volume data collection in manufacturing environment. Expert in delivering design/test data for test vehicles from product introduction up to test vehicle certification, supporting high volume manufacturing throughout the life cycle of the product. Technical lead for Product test in pre-/post-si design validation for nanoscale technologies; Developing test methodology, pre- and post-silicon validation platform for nanoscale device, circuit and system characterization at full chip environment deploying innovative tools and techniques utilizing hardware-software interaction and co-design.Delivered pre-Si and post-Si design validation and innovative solutions for test vehicle high volume wafer sort and packaged unit level data collection for process certification for Intel’s 22nm, 14nm, 10nm, 7nm, 5nm and beyond processes. Senior Member of and a reviewer of holds more than 30 technical journal and conference publications including JAP, APS, IEDM, etc.

Experience

1. Adjunct Assistant Professor

   Portland State University

   Dec 2020 — Present · Portland, OR, US

   Dept of Electrical and Computer Engineering

Education

• University of California, Riverside

  MS, Electrical Engineering

  2006 — 2009

• Bangladesh University of Engineering and Technology

  MSc, Nanoelectronics and optoelectronics

  2003 — 2005

• University of California, Riverside

  PhD, Electrical Engineering

  2006 — 2010

• Purdue University

  Certificate, Nanotechnology

  2009 — 2009

• Bangladesh University of Engineering and Technology

  BSc, Electrical and Electronics Engineering

  1997 — 2003