Khirul Anam
Application Engineer @Keysight Technologies
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WORK HISTORY
Application Engineer @Keysight Technologies
US
Developed, debugged & supported ATE test programs (parametric & silicon photonics) from NPI through HVM ramp• Analyzed device and test data to identify yield detractors and optimize test methodologies• Increased test throughput while maintaining optimal yield and product quality targets• Performed system-level fault-isolation and provided solutions, collaborating with cross-functional engineering teams• Partnered with R&D and Marketing teams to provide technical sales support, exceeding targets by 500%• Served as the technical interface between Keysight and semiconductor customers• Delivered training to junior engineers and customers on test platforms and software
EDUCATION
The University of Texas at San Antonio
Doctor of Philosophy - PhD, Electrical Engineering
DRMC - Dhaka Residential Model College
Secondary School Certificate
Ahsanullah University of Science and Technology
Bachelor of Engineering (B.Eng.), Electrical and Electronic Engineering
DRMC - Dhaka Residential Model College
Higher Secondary Certificate
ABOUT KHIRUL ANAM
Semiconductor technology engineer specializing in advanced logic nodes (FinFET & GAA, 7nm–1.8nm), driving yield, manufacturability, and performance at scale. At Intel, improved 7nm yield by ~40% from ramp to HVM through DOE-driven optimization, statistical modeling, and deep device-level failure analysis—preventing major excursions and line-down events while achieving multi-order defect density reduction.Currently at Keysight Technologies, supporting parametric and silicon photonics ATE development from NPI through production ramp, increasing test throughput while protecting yield and product quality. Serve as the technical interface between engineering, R&D, and customers, delivering scalable test solutions and exceeding technical sales targets.Ph.D. in Electrical Engineering with strong expertise in device physics, 2D/3D modeling for non-volatile memory (PCM) & logic gate (Electrostrictive field-effect transistor), electrical/material characterization, and high-speed, low-power device innovation. Passionate about solving complex silicon challenges where physics, data, and execution intersect to ship world-class hardware.Summary:1. Owned advanced semiconductor technology nodes (FinFET & GAA) 2. Responsible for Intel’s 7nm to 1.8nm nodes, enabling global technology transfer3. DOE: Improved ~40% yield on 7nm process from ramp to HVM4. Developed, debugged, and supported ATE test programs for parametric & silicon photonic tests5. Introduced 4+ NPI for 7nm to 1.8nm process nodes6. Conducted failure analysis (FA) to detect and identify process marginalities & inline issues7. Model-based problem solving to drive solution for 5 excursion/ 2 line down events8. 2D/3D modeling & simulation: Proposed sub-60 mV/decade device9. Extensive knowledge, research & journal on non-volatile memory devices10. Experienced in device physics, simulation, synthesis, and characterization
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