Kevin Freitas

About Kevin Freitas

I am a dedicated, hardworking, self-motivated engineer with a passion for learning and…

Experience

1. Senior Fpga Design Engineer

   科磊股份有限公司

   Dec 2021 — Present

   FPGA design and test. Developed software for FPGA control and testing. Worked with board designers to specify FPGA interfaces and helped troubleshoot boards. Worked with software engineers to troubleshoot product level software-Extensive use of Xilinx AXI VIP to test the custom AXI4Lite slave modules-Took ownership of an entire Kintex UltraScale FPGA design with legacy IP. Created a simulation which includes the Xilinx AXI VIP, fixed bugs, ported additional legacy IP, added new features and resolved complex timing issues-I made FPGA design changes in order to significantly reduce the circuit board BOM cost, resolve supply chain issues and reduce software complexity and load-Implemented PCIe x4 Gen3 (8GT/s) over Thunderbolt 3 using the Xilinx AXI Bridge for PCI Express Gen3 Subsystem. I used pciutils lspci to verify the PCIe endpoint enumeration and Jungo DriverWizard to verify AXI4Lite register reads and writes over PCIe in Windows. I used lspci to verify the PCIe endpoint enumeration in Linux-Implemented AXI Chip2Chip (both AXI4 and AXI4Lite) with Aurora 1 lane, 10.3125 Gbps over optical SFP+-Implemented IBERT 8 lanes, 10.3125 Gbps per lane for board testing over optical SFP+. Customized the IBERT design to drive the SFP+ TX Disable and Rate Select-Created AXI4Lite slave module ADC and DAC interfaces, simulated the design with the Xilinx AXI VIP, verified the design with the ADC and DAC eval boards and Xilinx KCU105 Kintex UltraScale FPGA board-Created a design including a C application running on bare metal-Created a Kria UltraScale+ MPSoC design including a bare metal C application, DMA with the Xilinx AXI Central DMA, Aurora and AXI Chip2Chip-Created a Kria UltraScale+ MPSoC design including C applications running on PetaLinux, PYNQ application running on Ubuntu, DMA with the Xilinx AXI Central DMA, Aurora, AXI Chip2Chip and AXI IIC. Languages: Verilog, SystemVerilog, Python, TCL, BASH, C Tools: QuestaSim, Vivado, SVN, GIT, Vitis

Skills

• Verilog
• Signaltap
• Xilinx Ise
• Systemverilog
• Dac Interfaces
• Iserdes
• Bert
• Subversion
• Pcie
• Adc Interfaces
• Matlab
• Dma
• C++
• High Speed Digital
• Mgt
• Embedded Software
• Systems Engineering
• Ddr3 Memory Interface Core
• Aurora
• Gnu Make
• Ddr
• Timing Closure
• Embedded Systems
• Synplify Pro
• Field-Programmable Gate Arrays (Fpga)
• Sfp
• Systemc
• High Speed Interfaces
• Visual Studio
• Ibert
• Simulations
• Serdes
• Digital Signal Processors
• Oserdes
• Chipscope Pro
• C#
• Altera Quartus
• Axi
• Plda Pcie Core
• Gtx