Kethavath Rajitha
VLSI - Design and Verification Trainee Design Verification, RTL design, Verilog,System Verilog, UVM.
- Role
- Design Verification Engineer Trainee at Sumedha Institute Of Technology
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kethavath Rajitha
A Challenging position in a technical organisation where I can enhance my skills, knowledge and work hard the achieving goals of on organisation.
Experience
Design Verification Engineer Trainee
Sumedha Institute Of Technology
Sep 2023 — Present · Hyderabad, IN
Education
Govt. Polytechnic College
Diploma
2017 — 2020
Vidya Jyothi Institute Of Technology
Bachelor's of Technology
2020 — 2023
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