Keshav Patil
Low Power Silicon Digital Design Engineer | Ex-Intel
- Role
- Low Power Silicon Digital Design Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
Experience
Low Power Silicon Digital Design Engineer
Apr 2025 — Present · Bengaluru, IN
Education
National Institute of Technology Surat
Master of Technology (M.Tech.)
2016 — 2018
Gujarat Technological University (GTU)
Bachelor of Engineering (B.E.)
2013 — 2016
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