Kesavan Thangasamy

About Kesavan Thangasamy

I am a seasoned IC packaging design lead engineer at Intel Corporation, where I have been developing next generation package solutions from concept to tape-out for over six years. I have 20+ years of professional package and PCB design experience, working with various EDA tools and technologies across different domains and industries.My core competencies include HDI designs with micro vias, stacked via, and via-in-pad, high speed, multi-layer digital PCB designs, signal integrity solutions, PCB layer management, rigid, flex, and rigid-flex PCB design, assembly drawings, ICT data generation, fabrication documents, auto-routing, EMI/EMC, and DFM/DFT. I ensure the package solutions meet the requirements for quality, performance, and cost, and manage multiple designs concurrently, working with multi-disciplinary teams. My mission is to deliver innovative and reliable package solutions that enable Intel\'s leadership in the semiconductor industry.

Experience

1. Staff Design Engineer

   Arm

   Feb 2026 — Present

   I am an engineer at Arm specializing in IC package design and PCB design, focused on delivering high-performance, reliable, and manufacturable hardware solutions. My work bridges silicon and system-level implementation, ensuring signal integrity, power integrity, thermal efficiency, and overall design robustness across complex compute platforms.With hands-on experience in package substrate design, high-speed PCB layout, and hardware integration, I contribute to enabling next-generation compute solutions that power devices from edge to cloud. I collaborate closely with silicon, system architecture, and validation teams to translate design requirements into scalable and production-ready hardware.My core strengths include:• IC package design and substrate optimization• High-speed PCB design and layout• Signal & power integrity considerations• Cross-functional hardware collaboration• Design for manufacturability (DFM) and reliabilityI am passionate about advancing hardware innovation and building robust physical infrastructure that enables cutting-edge compute performance.

Education

• Dr. MGR Educational and Research Institute, Chennai, India .

  B.Tech, Electronics and Communication Engineering

  2005 — 2008

• Srinivasa Polytechnic, Trichy, India.

  DICE, Instrumentation and control Engineering

  1997 — 2000

Skills

• Pcb Design
• Cadence Allegro
• Dfm
• Dft
• Mentor Pads Layout
• Mentor Pads Logic
• Orcad Capture
• Cadence Specctra
• Mentor Expedition Layout
• Mentor Design Capture
• Cr5000
• Altinum
• Mentor Lpwizard (Library Development)
• Cam350
• Valor
• Emi
• Power Electronics Design
• Cadence
• Orcad
• Design for Manufacturing
• Modelsim
• Analog
• Signal Integrity
• Electronics
• Testing
• Embedded Software
• Allegro
• Schematic Capture
• Semiconductors
• Altium Designer
• Eda
• Embedded Systems
• Fpga
• Microcontrollers
• Verilog
• Hardware Architecture
• Firmware
• Vhdl
• Analog Circuit Design
• Debugging