Kensuke Yamamoto

About Kensuke Yamamoto

I am a Senior Staff Design Manager at Marvell Technology, where I worked as a core member to perform many different tasks in front-end design for multiple VLSI chips. I have more than 22 years of experience in the semiconductor industry, and my core competencies include all aspect of front-end design from RTL design, IP integration, formal/CDC check, design verification, DFT, FPGA prototyping to synthesis & STA.I am passionate about solving challenging problems, delivering high-quality results, and collaborating with teams to achieve shared goals.

Experience

1. Smts Silicon Design Engineer

   AMD

   Apr 2024 — Present · San Jose, CA, US

Education

• The University of Osaka

  Master of Engineering, Electrical Engineering

  2000 — 2002

• The University of Osaka

  Bachelor of Engineering, Electrical Engineering

  1996 — 2000

Skills

• Pcb Design
• Formal Verification
• Rtl Coding
• Semiconductor Industry
• Dft
• Functional Verification
• Vlsi
• Amba Ahb
• Pcie
• Verilog
• Logic Synthesis
• Systemverilog
• Sata
• Debugging
• Integrated Circuit Design
• Arm
• Uvm
• Vhdl
• Simulations
• Axi
• Integration
• Perl
• Eda
• Timing Closure
• Logic Design
• C
• Static Timing Analysis
• Tcl
• Semiconductors
• Soc
• Ic
• Rtl Design
• Fpga
• Asic