Keith Jangryul Kim
Memory Architect Asic Mss (Memory Sub System) @NVIDIA
San Jose, CA, US
EMAILS
k•••••••@nvidia.com
MOBILE NUMBERS
+91 *********19
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WORK HISTORY
Mar 2023 — Present
Memory Architect Asic Mss (Memory Sub System) @NVIDIA
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Santa Clara, CA, US
ABOUT KEITH JANGRYUL KIM
DRAM Product engineering HBM / DDR Product Planning and micro spec architecture developmentJEDEC specification development and JEDEC chairman Director and DRAM Technology Team leader
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