Keerthika U
Lead Engineer @ HCLTech | Analog Layout Design
- Role
- Lead Engineer at HCLTech
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Keerthika U
A total of 4+ years of analog layout experience-Intel7nm, Intel5nm, Intel22nm technology expertise-Cadence Virtuoso were utilized as tools-Worked on blocks like HSIO,BGR,FIVR,Clock, etc-Expertise in implementing verification flows such as DRC, lVS, EM, IR, RV, and HV-Experienced in floorplanning, power routing, clock routing, and EM and IR analysis.
Experience
Lead Engineer
Oct 2025 — Present
Education
Sri Sai Ram Institute of Technology (Sairam Group of Institutions)
B.E, ECE
2017 — 2021
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