Keerthana M
SOC Design Engineer at Intel Corporation
- Role
- Senior Design Engineering at 高通
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
About Keerthana M
5 years of experience working on DFT features like MBIST Tap. Hands-on mbist Block level & SoC level pattern generation also validated them before signing off. Basic understanding on SCAN, BSCAN and IJTAG network integration methodology using tessent. Good hands-on on industry tools like Mentor, Synopsys. Strong engineering professional with a Master of Technology - MTech focused in Vlsi from National Institute of Technology Warangal.
Experience
Senior Design Engineering
Jan 2026 — Present · IN
Education
National Institute of Technology Warangal
Master of Technology - MTech, Vlsi
2018 — 2020
Careers for engineering students
Bachelor of Technology - BTech, Electronics and Communications Engineering
2014 — 2018
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