Kedar Karandikar

About Kedar Karandikar

Senior technical leader with experience of 16 years in the domain of Server SOCs. Extensive experience in Pre-Silicon and Post-Silicon Validation in the domains of SOC Architecture, Cache Coherency and Interconnect protocols.

Experience

1. Senior Distinguished Engineer

   Ampere

   Feb 2024 — Present · Santa Clara, CA, US

   Key technical leader in Ampere - Emulation (Pre-Silicon) and System Level Validation lead (Post-Silicon). Technical lead for CPU validation- Proven track record of building and leading high-performing teams in domains of Design verification and Post-Silicon validation- Responsible for evaluation and selection of newer technologies for improving verification- Experience driving execution of multiple projects from its inception to its tape-out and then from Silicon bringup through PRQ- Technical achievements included building verification infrastructures from scratch, developing Bare-metal verification frameworks and conceptualizing innovative solutions for accelerating bug hunting- Key member of Ampere\'s Silicon bringup team for multiple generations of SOC due to knowledge of system level flows and strong debug skills- Extensive experience of ARM Architecture in areas of CPU, Cache coherency, Mesh interconnects, Bus protocols (CHI, AXI, etc), System boot flows and some of PCIE, DDR.

Education

• K.J. Somaiya College of Engineering, University of Mumbai

  Bachelor of Engineering, Electronics and Telecommunication

  2003 — 2007

• Georgia Institute of Technology

  Master of Science in Electrical and Computer Engineering, Computer Architecture

  2007 — 2009

Skills

• Systemverilog
• Emulation
• Computer Architecture
• Processors
• Simulations
• C++
• Fpga Emulation
• Verilog/Vhdl
• Ddr Memory Technology
• Inter-Processor Routing and Networks
• Cuda
• Perl
• Logic Synthesis
• Python
• Debugging
• Rtl Verification
• Verilog
• Rtl Design
• X86
• C
• Simics
• Pcie
• System Architecture
• Intel
• System on a Chip (Soc)