Kedar Hotkar

About Kedar Hotkar

As a Manager in Process Design kit IQA and Physical Verification at Samsung Electronics, I have over 20 years of experience pdk, pv and analog layout I have successfully completed multiple tapeouts of SOC, subsystem, and block level designs, ensuring compliance with design rules, layout versus schematic, design for manufacturability, fault tolerance, and reliability standards.PDK development - pcell migration from 6.1.8 to 23.1.0 virtuoso tool for 130nm. PCell development (2nm 45nm 55nm). PVS and SVRF rule deck writing.PDK QA - DRC QA, Regression test cases. PCell verification and Integrated QA. My core competencies include, PV run flow, scripting, and analog layout design. I have extensive knowledge and skills in using CalibreDESIGNrev, Innovus, and ICC compiler tools, as well as Cadence skill language. I have also contributed to the development and quality assurance of process design kits and design rule checks. I am passionate about delivering high-quality and innovative solutions for the semiconductor industry, and I enjoy working with a talented and collaborative team at Samsung Electronics.

Experience

1. Senior Technical Manager (Pdk)

   HCLTech

   Jun 2024 — Present · Bengaluru, IN

Education

• Shri Guru Gobind Singhji Institute of Engineering and Technology, Vishnupuri, Nanded

  Master’s Degree, Electronics

  2006 — 2007

• Walchand Institute of Technology, Solapur

  Bachelor’s Degree, Electronics

  2000 — 2004

Skills

• Spectre
• Lvs
• Cadence
• Ic
• Very-Large-Scale Integration (Vlsi)
• Mixed Signal
• Analog Circuit Design
• Eda
• Soc
• Design Rule Checking (Drc)
• Drc
• Integrated Circuit Design
• Cadence Virtuoso
• Vlsi
• Analog
• Cmos