Kavya Koduri
Aspiring Design Verification Engineer | Verilog | SystemVerilog | UVM | Functional Coverage | Assertions | AMBA Protocols
- Role
- Trainee at Maven Silicon
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kavya Koduri
Design Verification Engineer (Fresher) with hands-on experience in SystemVerilog, Verilog, and UVM-based verification methodologies.I have worked on protocol-level verification projects including APB-SPI interface verification using UVM, involving development of drivers, monitors, sequencers, scoreboards, constrained-random stimulus, and functional coverage.Currently, I am working on UART-APB verification, focusing on transaction-level modeling, protocol checking, assertions, and coverage-driven verification.Strong foundation in digital electronics and verification concepts such as testbench architecture, functional coverage, assertions (SVA), and debugging using waveform analysis.Passionate about semiconductor and VLSI verification, and actively seeking entry-level Design Verification / ASIC Verification opportunities where I can contribute and grow as a design verification engineer.
Experience
Trainee
Jun 2025 — Present · Bengaluru, IN
Education
Narayana Junior College, Vijayawada
Intermediate
2019 — 2021
SRK Institute of Technology
Bachelor of Technology - BTech, Electronics and communication engineering
Bhashyam High School, Ongole
10th SSC
2018 — 2019
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.