Kavya Gaddipati
- Role
- Physical Design Engineer at Intel
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Kavya Gaddipati
Highly skilled IC Layout Engineer with over 5 years of experience in designing and…
Experience
Physical Design Engineer
Jan 2020 — Present
Design tasks for Intel’s Xeon line of server products supporting on 18A process. Working on spice level netlist to gdsII Physical Design of LVDS Transmitter and its subblocks using RibbonFET and PowerVia technology Performing analog layout of driver block and its hierarchies using Cadence Virtuoso Layout editor Proficiency in layout floor planning, hierarchy layout assembly, placement, dummy insertion, matching techniques Electrically analyze, simulate and verify interconnect decisions for electrically correct layout designs in real time using the Cadence Virtuoso EAD tool Physical verification- resolved opens/Shorts, Fixing Base and Metal DRC/LVS using Real time Calibre and density related violations in all my blocks. Work with Designers on Understanding RV- EM IR drop analysis reports from Totem, Redhawk and fixing hotspots in layouts Working on tape out flow and delivering IP’s supporting 7nm Fin FET process to the customers
Education
Anna University Chennai
Bachelor's degree, Electrical, Electronics and Communications Engineering
2012 — 2016
Arizona State University
Master of Science, Electrical and Electronics Engineering
2017 — 2019
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