Kavita Balakavi

About Kavita Balakavi

Overseeing the team and spearheading enablement initiatives across a suite of Edge Accelerating. Sensor Hubs and Automotive IP Portfolio. Drive execution, playing a pivotal role in providing unique IPs to our SOC collaborators. Enhanced team productivity by 50% and minimized the workload on Frontend and Backend execution for designers.Integrating AI bots for enhancing process efficiency! Educating organizational engineers on adopting AI and ML strategies for daily tasks.Directed projects involving advanced process nodes, both in-house and with external foundries. Conducted project milestone reviews with design, validation teams, ensuring quality as focal point.Created Splunk dashboards to monitor key quality indicators. Guided the team in executing essential change requests for clients. Established a project layer infrastructure for execution, benefiting over 20 IP teams within the organization. This initiative has enhanced organizational efficiency by at least 35-40%!Before this role, I served as the Lead SD Engineer in Physical Design execution for networking SoCs (System on Chip), managing a highly complex Memory Subsystem that included integrating DDR3 PHY from SNPS. My experience also spans the DFT domain, covering Execution and TFM roles.My contributions spanned various areas, including: establishing and expanding projects, developing design automation and methodologies, engaging in validation and verification, automating processes, managing projects and teams, integrating front-end systems, implementing back-end/SD solutions, executing projects, and providing application support.Areas of expertise include : System on Chip (SOC) Design flowsFront end Implementation and supportBackend SD domain knowledge and executionProject setup and proliferationDFX Feature Implementation including Scan, JtagATPG Flow development and execution, Pre-Silicon validation Post-Silicon Test content debugApplication supportExtended Expertise in : Engineering ManagementProject ManagementExecution & Engineering ProcessLiason between IP team, SOC, Tool vendors and other stakeholders

Experience

1. Soc Design Engineering Manager

   Intel

   Dec 2022 — Present · Bengaluru, IN

   Managing an engineering team in the execution of Intellectual Property (IP) across both Front End and Back End domains in ASIC design, we delved into the nuances of Low Power design. Our journey encompassed a variety of IPs, including Sensing Hubs, Touch Controllers, broadening our technological horizon.We enhanced efficiency by 40%-50% through the implementation of dashboards and Splunk automation for milestone reviews, significantly reducing the need for manual effort by designers. Additionally, we pioneered AI/ML automation initiatives, leveraging an AI Engine to streamline processes, and conducted demos across design teams to inspire a similar mindset.In parallel, focused on the professional development of talented engineers, mentoring, guiding, and coaching them in ASIC Design flows. This included comprehensive exposure to both Frontend and Backend Design, Low Power techniques, and Methodology topics, fostering their career progression.Actively pursuing process enhancement opportunities by interacting with vendors, stakeholders, and project teams. In collaboration with IP and SOC teams from RTL to TapeOut, my role encompasses efficiently communicating project developments, overseeing execution hurdles, monitoring advancements, pinpointing constraints, and applying solutions throughout the workflow.

Education

• The University of New Mexico

  Master of Science (MS), Computer Engineering

• Osmania University

  B.S, Electrical