Kavit Patadia

About Kavit Patadia

12 years of strong experience in Physical design Implementation, execution, and Methodology ==> Led the CPU L2 cache development work from PD Side for feasibility and convergence of the entire hierarchical subsystem.==> Strong Experience in cutting-edge technology (including tsmc 3nm/Samsung 3gap) on PPA critical and highly complex CPU/GPU Designs.==> Have successfully done 11+ Tape outs and supported multiple projects in ECO convergence concerning STA, EMIR, PDV, formal verification, low power checks ==> Hands-on experience in Cadence/Synopsys Synthesis, PNR, and signoff tools ==> Actively coding in tcl/Linux/tool commands to be more efficient and to develop small automation ==> Skilled in PPA optimizations, convergence & TAT improvements in synthesis, and PNR from all aspects ==> Possess good debugging, mentoring, coaching, and leadership skills ==> Proficient at collaborating and communicating effectively with stakeholders across different sites & domains

Experience

1. Senior Physical Design Engineer

   NVIDIA

   Apr 2024 — Present · IN

Education

• Gujarat Technological University

  Bachelor of Engineering (B.E.), Electronic and Communications

  2008 — 2012

Skills

• Physical Design
• Tcl
• Cmos
• Timing
• Tcl-Tk
• Cadence
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Very-Large-Scale Integration (Vlsi)
• Linux
• Shell Scripting
• Perl Script
• Verilog
• Perl
• Eda
• Timing Closure
• Static Timing Analysis
• Digital Electronics
• Synopsys Tools
• Functional Verification
• Asic
• Layout Versus Schematic (Lvs)
• Primetime