Kaveh Sadeghikhah

Asic Fpga Engineer @Alphawave Semi

Ottawa, ON, CA
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WORK HISTORY

Apr 2024 — Present

Asic Fpga Engineer @Alphawave Semi

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Ottawa, ON, CA

EDUCATION

N/A

University of Regina

Master of Applied Science, Electronic Systems Engineering

2007 — 2011

Islamic Azad University

Bachelor's degree, Electrical and Electronics Engineering

2015 — 2019

Islamic Azad University, Science And Research Branch

Master of Science (M.S.), Electrical and Electronics Engineering

ABOUT KAVEH SADEGHIKHAH

A highly skilled ASIC/FPGA Engineer with hands-on experience in designing, implementing, and verifying digital signal processing algorithms, high-speed protocols, scientific computing, interfacing different protocols/peripherals on FPGAs, and High-Level Synthesis design (HLS) of digital circuits and algorithms on FPGAs/Embedded Systems. Experiences- Interfaced different protocols and peripherals such as a Temperature Sensor, RS232, SPI, I2C, GPS, DAC, DDR3 RAM, LCD, PCIe & Ethernet - Designed and Implemented QRD algorithm on an MPSoC Xilinx UltraScale+- Designed and Implemented Systolic Array Processor on an MPSoC Xilinx UltraScale+- Designed complex floating-point matrix calculations in FPGA - Designed and implemented different algorithms on FPGA including FFT, FIR Filter, AM modulation, IIR Filter, Convolution, Moving Average Filter, Pulse Detector, and Frequency Estimator - Hands-on experience with Xilinx Zynq UltraScale/UltraScale+ MPSoC, Versal ACAP devices, and Zynq - Floating-point and fixed-point design and verification in FPGAs - Provided HLS design flow of FPGAs for various circuits - Worked with Xilinx design toolsets such as ISE, Vivado, Vitis-HLS, and Vitis - Proven expertise with AXI4-MM, AXI4-S, & AXI4-Lite protocols - Full RTL Design - Design Integration with Makefiles - Scripting using Python, Bash, & Tcl - Written VHDL/Verilog/SystemVerilog design and testbench codes - Generated RTL hardware IP cores in Vitis-HLS - Written C testbench in Vitis-HLS - Knowledge of front-end tools (Verilog simulators, CDC/RDC checkers, Logic Equivalence Check (LEC), low-power static checkers, linting)- EDA tools such as VCS, VCLP, Spyglass Lint, Verdi, Fusion Compiler, & Design Compiler- Accelerated algorithms with the help of the Xilinx Vitis platform - Integration of different chunks with Makefile - Used C/C++ for accelerating compute-intensive algorithms on embedded platforms - Implemented ML/DL algorithms: Support Vector Machine (SVM) and Artificial Neural Networks in FPGA Interested in the following fields- FPGA/Embedded Design and Implementation - Machine Learning, Deep Learning, Neural Networks, and their Applications in Computer Vision - Digital Circuits, Computer Architecture, Computer Organization, and Data Structures - Analog/Digital/Mixed-Signal and VLSI Circuits Design Also- Goal-oriented and meticulous personality to reach maximum efficiency - Able to work under pressure and cooperate with team members to meet the deadlines - Collaboration with software developers & system designers for integration of the project

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Kaveh Sadeghikhah — Asic Fpga Engineer at Alphawave Semi in Ottawa, ON, CA | Unifers