Kaushik Manikandan Parasuraman
Design Verification Engineer @Meta
San Jose, CA, US
EMAILS
MOBILE NUMBERS
+91 *********19
Signup · Get unlimited contacts
WORK HISTORY
Oct 2024 — Present
Design Verification Engineer @Meta
View department →
San Francisco, CA, US
EDUCATION
2017 — 2018
North Carolina State University
Master of Science - MS
2013 — 2017
National Institute of Technology Tiruchirappalli
Bachelor of Technology - BTech
SKILLS
ArmModelsimInstrumentationEmbedded SystemsRtl VerificationCudaImage ProcessingTeamworkTeam ManagementNeural NetworksVhdlMicrosoft Visual Studio C++C++Digital Circuit DesignResearchFuzzy LogicControl Systems DesignElectronicsTeam LeadershipComputer ArchitectureCustomer ServiceVerilogProgrammingMicrosoft OfficeApplication-Specific Integrated Circuits (Asic)Signal ProcessingSimulinkLabviewEvent ManagementArduinoSynopsys Tools
ABOUT KAUSHIK MANIKANDAN PARASURAMAN
I am currently working as a pre-si IP verification engineer of the caching controller IP part of the Xeon coherent fabric.
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.