Kaushik Anugu
Soc Design Engineer @Apple
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WORK HISTORY
Soc Design Engineer @Apple
Munich, DE
EDUCATION
St. Joseph’s Convent High School
High School
Vellore Institute of Technology
Bachelor's degree, Electronics and Communications Engineering
Technical University of Munich
Master of Science, Electrical and Computer Engineering
ABOUT KAUSHIK ANUGU
Good understanding of CMOS Logic Design. • Academic and Industrial experience in the ASIC digital design sign-off flow with industry-standard EDA tools. • Proficient in VHDL and Verilog. • Hands-on experience in the full custom layout of Digital and Analog blocks by contemplating trade-offs such as Power, Performance and Area constraints. • An avid researcher and a team player with good interpersonal skills. Programming Languages: Python, C, VHDL, Verilog, TCL, Perl, SQL, JMP Scripting Language(JSL). Tools: Synopsis ICC, Synopsis DC, Synopsys FC, Cadence Virtuoso, Synopsys PrimeTime, Hspice, Multisim, Xilinx ISE, GIT, JMP, LaTeX. Databases: MySQL, MongoDB OS: Windows, iOS, Unix Design Skills: VLSI Design, RTL Design, Physical Design, Custom IC Design, Analog and Digital Layout, Layout Cost functions, Signal Integrity, Static Timing Analysis, Clock Domain Crossing, Clock Tree Synthesis.
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