Kaushal Karkera
Senior Physical Design Engineer at Astera Labs || Ex-Intel
- Role
- Senior Physical Design Engineer at Astera Labs
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Kaushal Karkera
Technical Skills:EDA Tools: Synopsys (Design Compiler, Fusion Compiler, StarRC), PrimeTime, IC Validator, ICC-II, Cadence Virtuoso Layout Suite EAD.Simulator: HSpice, Wave viewer, Spectre, ModelSim.Design and Applications: MATLAB, SolidWorks.Hardware Definition Language: Verilog.Scripting Language: Tcl, Python, Shell.
Experience
Senior Physical Design Engineer
Sep 2025 — Present · San Jose, CA, US
Education
Ramrao Adik Institute of Technology
Bachelor of Engineering - BE, Electronics engineering
2015 — 2019
Pace junior science college
HSC, Science
2013 — 2015
Arizona State University
Master's degree, Electrical engineering
2019 — 2021
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