Kathir S
Aspiring VLSI Engineer | RTL Design, Verification & Physical Design | Verilog, SystemVerilog | Embedded Systems & IoT Developer | Student at Anna University | Open to Internships & Collaborations
- Role
- Rtl Design and Verification Engineer at Zepto Logic Technologies Pvt Ltd
- Location
- Coimbatore, IN
- LinkedIn followers
- 500 followers
About Kathir S
I am a final year Electronics and Communication Engineering student at Anna University Regional Campus Coimbatore, passionate about VLSI Design, Embedded Systems, and IoT. With hands-on experience in Verilog, SystemVerilog, UVM, and tools like Cadence, Vivado, Questa ModelSim, and MATLAB, I specialize in RTL design, verification, and system development. My expertise also extends to firmware development and automation using STM32, ESP32, and Raspberry Pi. Key Projects: RISC-V Processor Implementation using Verilog, optimizing pipeline stages and ALU functions. AI-Powered Electronics Assistant (Electro AI) to help engineers with component selection and project planning. IoT-based Smart Automation System using ESP8266 and Telegram for remote appliance control. Career Goals: I aim to contribute to cutting-edge projects in VLSI and Embedded Systems, leveraging my knowledge of RTL design, IP development, and verification methodologies to develop innovative semiconductor and IoT solutions. Future Goals: Committed to continuous learning, I focus on emerging technologies in VLSI and IoT, actively working on projects that bridge theoretical knowledge with real-world applications. My goal is to push the boundaries of technology while mentoring and sharing knowledge with aspiring engineers. Let’s connect to explore opportunities in VLSI and Embedded Systems!
Experience
Rtl Design and Verification Engineer
Zepto Logic Technologies Pvt Ltd
Jun 2025 — Present · Coimbatore, IN
Working real-time projects involving digital design, RTL coding, and functional verification aligned with industry practices.I worked on several VLSI and SoC projects, including Phase Value Detection, DAS in SoC, Low Power Asynchronous FIFO, Dadda Multiplier, Squaring Circuit, and BIST implementation. I also contributed to designing an 8-bit Integer Restoring Divider and a heartbeat detection system using ECG signals with DSNN.Collaborating on IP-level RTL design and verification tasks gaining hands-on exposure to SoC methodologies and design workflows.
Education
Anna University
Bachelor of Engineering - BE
2022 — 2026
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