Kasi Ch
SoC Low power Design/Verification|Post Silicon Validation|Ex-Qualcomm
- Role
- Silicon Product Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kasi Ch
Experienced in arm based soc low power Design, verification and validation. Key skills include UPF modelling, power estimation, PARTL and PAGLS simulations. Have worked on post silicon validation on ATE platform and supported AMS/HSIO bench validation.
Experience
Silicon Product Engineer
Sep 2022 — Present · Bengaluru, IN
Education
Victoria University
M.E, Micro electronics
2004 — 2005
Karunya Institute of Technology
B.E, Electronics and Communication Engineering
1999 — 2003
Skills
- Very-Large-Scale Integration (Vlsi)
- Soc
- Debugging
- Silicon
- Asic
- Systemverilog
- Atpg
- Analog
- Application-Specific Integrated Circuits (Asic)
- Integrated Circuit Design
- Simulations
- Verilog-a
- Verilog
- Rtl Design
- Mixed Signal
- Vlsi
- Functional Verification
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