Kashyap Kansara
Principal Engineer- Silicon Design at Microsoft
- Role
- Principal Engineer Silicon Design at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Kashyap Kansara
ASIC physical design Lead with 10+ years of experience.Experience on Synopsys, Cadence & Mentor tool chains.Expertise on 16nm, 28nm, 40nm, 65nm, 90nm & 130nm for Synthesis, PNR, STA, Physical verification, IR drop & Power Analysis, CTS, DFT & Low Power Implementation. Exposure in Synopsys ICC, PT-SI, Star RC-XT, Cadence EDI & Calibre DRC LVS.Specialties- Design planning / Die size estimation - Power Structure Design- Complete flow development- Clock Tree Synthesis- Timing & Area Optimization- Low Power Implementation- Sign Off STA- Physical Verification- Client Communication & Business Development
Experience
Principal Engineer Silicon Design
Feb 2023 — Present · Bengaluru, IN
Education
Vishwakarma Government Engineering College
BE, Electronics & Communication
2002 — 2006
Kameshwar High School
High School, Science
Skills
- Lvs
- Physical Design
- Scripting
- Soc
- Perl
- Drc
- Vlsi
- Low-Power Design
- Pnr
- Static Timing Analysis
- Vhdl
- Debugging
- Design Planning
- Fpga
- Asic
- Physical Verification
- Verilog
- Integrated Circuit Design
- Clock Tree Synthesis
- Very-Large-Scale Integration (Vlsi)
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