Kashika Hingorani
Senior Analog Validation Engineer at NXP Semiconductors || M.Tech BITS Pilani || B.Tech IGDTUW
- Role
- Analog Validation Engineer -g2 at NXP Semiconductors
- Location
- Delhi, DL, IN
- LinkedIn followers
- 500 followers
Experience
Analog Validation Engineer -g2
Apr 2024 — Present
Education
Carmel Convent School - India
High School Diploma
2011 — 2018
INDIRA GANDHI DELHI TECHNICAL UNIVERSITY FOR WOMEN
Bachelor of Technology - BTech
2018 — 2022
BITS Pilani Work Integrated Learning Programmes
Master of Technology - MTech
2024
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