Kartik M K
CPU verification
- Role
- Cpu Verification at Tenstorrent
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Kartik M K
Currently pursuing Master in Electrical Engineering (Digital VLSI) at San Jose State University.Expertise in Front End Digital Design and Verification.4 years of rich academic experience in Digital design and verification. Hands on experience working with Verilog, SystemVerilog (UVM) for RTL design and verification.Tools: Design Compiler, VCS, Vivado, ISE Design Suite, ModelSim, Cadence Encounter, C programming, Keil, Masm, MATLAB. Protocols: AXI, AHB, APB, OCP, SPI, I2C, JTAG, UART.Specialties: VerilogVHDLSystemVerilog (UVM)Gate Level Simulation (GLS)Static Timing AnalysisPlace and RouteD AlgorithmScan Based Testing AssertionsFunctional / Code Coverage
Experience
Cpu Verification
Jul 2024 — Present · Austin, TX, US
Education
St Xavier High School
High School, English
1997 — 2008
San José State University
Master’s Degree, Electrical, Electronics and Communications Engineering
2015 — 2017
S G Balekundari Institute of Technology
Bachelor’s Degree, Electrical, Electronics and Communications Engineering
2010 — 2014
Skills
- Fpga
- Asic
- Microsoft Word
- Research
- System Verilog
- Vhdl
- Application-Specific Integrated Circuits (Asic)
- C
- Linux
- Integrated Circuit Design
- Matlab
- Perl
- Eda
- Management
- Verilog
- Leadership
- Static Timing Analysis
- Synopsys Tools
- Microsoft Excel
- Powerpoint
- Uvm
- Microsoft Office
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