Karthik Veerakumar

About Karthik Veerakumar

Skilled multi-disciplinary engineer with experience in physical design implementation…

Experience

1. Soc Design Engineer

   Intel

   Dec 2015 — Present

   Experience with all aspects of design closure as well as signoff flows. Owned 20% of packet processing IP within NAC subsystem for basestation chip enabling 5G on Intel 10nm process node. Product announcement below. Owned floorplan for 2 IPs on a smart NIC SoC, totaling 17% of total SoC area. Both IPs had unique set of challenges which needed a lot of trials and custom solutions to build a solid floorplan for successful tapeout. This project was on TSMC 7nm process node. Product announcement below: https://venturebeat.com/2021/10/27/intel-partners-with-google-to-deploy-mount-evans-asic-based-gpu/ Experience of working with cross-functional as well as cross -geographical teams for multiple projects at the same time. Provided technical guidance to a team of contract workers for achieving design closure on 4 partitions.

Skills

• Analog Circuit Design
• C++
• Synopsys Design Vision
• Asic
• Cadence Encounter
• Synopsys Primetime
• Logic Synthesis
• I2s
• C
• Physical Design
• Logic Design
• Application-Specific Integrated Circuits (Asic)
• Soc
• Cadence Ade Xl
• Modelsim
• Static Timing Analysis
• Simulink
• Vcs
• Mixed Signal
• Perl
• Spectre Rf
• Verilog
• Spectre
• Semiconductors
• Mentor Calibre
• Synopsys Ic Compiler
• I2c
• Cadence Virtuoso
• Audio Precision
• Matlab
• Unix Shell Scripting
• Cmos
• Place & Route