Sai Karthik Reddy Pala
VLSI Design & Verification Engineer | Hands-on Verification in PCIe Controller (EP & RP), AXI DMA, AXI Interconnect, APB & I2C | Skilled in SystemVerilog, UVM, Digital Design, Scripting (Python), Gvim Editor & MS Excel.
- Role
- Design Verification Engineer at ACL Digital
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
Experience
Design Verification Engineer
Nov 2025 — Present · Hyderabad, IN
Education
Mother Teresa Vidyalayam
Secondary School Certificate (TS), 8th to 10th class
New Song Community School
Primary School , Lower KinderGarten to 7th Class
Vasavi College of Engg
Bachelor of Engineering - BE, Electronics and Communications Engineering
Narayana Junior College
Intermediate , Mathematics,Physics & Chemistry
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