Karthikkeyan Ar
VLSI Engineer | ASIC Design @ Capgemini | Ex-Wipro | Ex-Jio | Ex-Caliber
- Role
- Professional Ii at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Karthikkeyan Ar
Expertise in writing and integrating synthesizable RTL models using VerilogKnowledge in the FPGA design flow, 5G concepts and OOPSWorking Experience in using industry-standard EDA tools for front-end design and verificationSkilled in designing Micro Architecture for IP\'sGood understanding in the Multi-block design and using Lint, CDCExperience in writing Testbench using Verilog and System VerilogKnowledge in UVM, IP Verification Planning and Coverage
Experience
Professional Ii
Jul 2022 — Present · Bengaluru, IN
Role - ASIC Design Client - Qualcomm, US
Education
Dr.Mahalingam College of Engineering & Technology
Bachelor of Engineering (BE), Electronics & Communications Engineering
2009 — 2013
M.P.Nachimuthu M.Jaganaathan Engineering College
Master's degree, VLSI Design
2014 — 2016
Vidhyaa Vikas, Thiruchengode
HSLC, Vocational - General Machinist
2007 — 2009
Saradha Vidhayalaya Matric. Hr.Sec. School
SSLC
1998 — 2007
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