Karthik Byrasandra Nagaraja Rao

About Karthik Byrasandra Nagaraja Rao

SUMMARY • Motivated Electrical Engineer with 7 years of professional experience…

Experience

1. Senior Physical Design Engineer

   Qualcomm

   Sep 2021 — Present · Santa Clara, CA, US

   Executed full physical design flow for DDR blocks across advanced nodes (4nm, 3nm, and 2nm), includingFloorplanning, placement, CTS, routing, and timing closure.• Developed optimized Floorplans for high-speed DDR blocks, balancing congestion, timing, and power across sub-5nmtechnologies.• Achieved timing closure across multiple corners and modes using advanced STA techniques in PrimeTime, resolvingcomplex setup/hold violations in high-speed DDR paths.• Optimized high-speed DDR PHY interface layout to meet aggressive PPA targets, leveraging advanced node-specifictechniques for signal integrity and performance.• Collaborated with cross-functional teams to integrate DDR subsystems into SoCs, ensuring timing closure and physicalverification across multiple corners and modes.• Automated physical design tasks using TCL and shell scripting, streamlining flows and reducing turnaround time for4nm/3nm/2nm tapeouts.• Performed power analysis and reduction using RedHawk, achieving significant dynamic and leakage power savings inDDR designs at sub-5nm nodes.• Implemented hierarchical design strategies and block-level partitioning to manage complexity and scalability of DDRIPs in 2nm designs.• Supported late-stage ECOs and debug cycles, ensuring minimal disruption to project timelines and maintaining qualityacross multiple tapeouts.