Karthik Sundararaman

About Karthik Sundararaman

Architected, managed and implemented DFT for numerous chips targeting mobile, GPUs and automotive industry. Cross functional expertise in talking to Product and Test teams handling issues at various stages of the bringup life cycle and yield improvement. Proven ability to communicate with senior management, estimate timelines and push through proposals and issues efficiently.

Experience

1. Dft Engineer

   NVIDIA

   Dec 2011 — Present · CA

   Lead Architect for DFx Emulation workflow DFT Lead for the first integrated phone chip. DFT Lead for the Automotive Tegra chips used for infotainment Responsibilities include Scan insertion, verification and post-silicon validation of a multi-million flop count design Compression planning and insertion for coverage improvement. Provide timing constraints and review waivers DFT scan architecture development including scripts for the custom compressor insertion along with Tmax spf bringup for the modem IP, boundary scan insertion and IP isolation with the rest of the chip for concurrent testing of IP (first time implemented at Nvidia) Created transactors for the Nexus (jtag like) protocol which used for pattern generation Silicon bringup of scan, atspeed, mbist, boundary scan and functional patterns Responsible for speed binning correlation of transition delay patterns with SLT and update specs to help with yield and post HTOL Implemented the (1500) jtag controller integration for the CPU core (multi voltage domain) along with the CDC waiver generation

Education

• University at Buffalo

  Masters, Computer Science and Engineering

  2002 — 2004

• SVCE

  BE, Computer Science and Engineering

  1998 — 2002

• University of Madras

  BE, Computer Science and Engineering

  1998 — 2002