Karthik Rao

About Karthik Rao

Poetic Bio:I am a sculptor of silicon symphonies and keeper of the sacred blueprints that breathe life into silicon realms. Born from the confluence of logic and lightning, I hold the exalted mantle of the hardware architect, crafting the unseen engines that power tomorrow’s visions. Beneath the endless glow of innovation’s beacon, I am the sentinel of circuits at Intel, guardian of the digital dawn.\"Classic Bio:14+ years of Experience in IP RTL Design & SOC Integration. Major Areas include- IP RTL Design Cycle from Specification Development to RTL Implementation and Verification closure, followed by SD Handoff, Timing Closure followed by Post Silicon Debug- SOC Integration (Responsible for IP Integration, Dangle Checks, CDC and Lint checks, UPF and Power Domain Crossing Checks etc- Experience with Low Speed and High Speed IO Protocols

Experience

1. Senior Ip Logic Design Engineer

   Intel

   Apr 2022 — Present · Bengaluru, IN

   Defined & implemented micro-architecture for various functional blocks of existing converged logical phy to support First Generation of PCIe with PAM4 encoding. Functional Blocks include, but not limited to OS Generation/Detection, TX Equalization, Precoding, Gray Coding, Scrambling, LTSSM, Error Logging, FSM Loggers, Deskew and other control logic. Helped achieve Latency Improvement of 25% compared to previous generation, while doubling the data rate. Responsible for meeting Power DCGE and DACGE targets. Handled various IP QC checks, timing closure along with validation support and meeting coverage targets. Taped out 2 chips successfully and supported PO and Post Si Debug for same. Working on micro-architecture definition and implementation for Next Generation of PCIe with PAM4 encoding for various functional blocks

Education

• Fatima High School, Vidyavihar, Mumbai

  LKG, UKG, I - VIII

  1992 — 2002

• University of Southern California

  Master's Degree, VLSI Design

  2013 — 2014

• Padua High School, Mangalore

  IX - X (Matriculation)

  2002 — 2004

• Nursery, Mumbai

  Nursery, Having Fun (amongst strangers)!

  1991 — 1992

• Manipal Institute of Technology

  BE, Electronics and Communication

  2006 — 2010

• Canara Pre University College

  XI - XII, PCME (Physics, Chemistry, Maths, Electronics)

  2004 — 2006

Skills

• Spi
• C/C++
• Rubik's Cube
• Logic Synthesis
• Asic
• System on a Chip (Soc)
• Validation
• Digital Design
• Xilinx
• Systemverilog
• Atpg
• Semiconductors
• Windows
• Keil
• C++
• Debugging
• C
• Hardware Architecture
• Ms Office Suite
• Html
• Cadence Ius
• Computer Architecture
• Keil Microvision
• Soc
• Pcb Design
• Simulation
• Python
• Dsp
• Vlsi
• Vhdl
• Digital Signal Processors
• Rtl Design
• Integrated Circuit Design
• Verilog
• Pspice
• Matlab
• Chess
• Very-Large-Scale Integration (Vlsi)
• Linux
• C