Karthik Govindarajan

About Karthik Govindarajan

Senior Verification Engineer with 14+ years of experience in IP and Sub-System verification, specializing in SystemVerilog, UVM, coverage closure, and pre, post-si debug. Expertise across AXI3/AXI4, MIPI-DSI, UFS 2.0/3.0, and serial protocols(I2C, I3C, UART, SPI). Strong background in building verification environments from scratch, modernizing legacy benches, mentoring teams, and developing AI-assisted automation tools to improve productivity.

Experience

1. Senior Design Verification Engineer

   Intel

   Dec 2018 — Present · Bangalore, IN

   Project 1: DCI (Direct Connect Interface) Debug IP• Reverse-engineered legacy IP and testbench; created verification plans.• Validated SOC propsed power-flow features; wrote feature testplans and testcases.• Identified legacy RTL bugs and multiple validation gaps.• Guided formal checks (Connectivity, Superlint, SEC) to closure.• Developed AI-powered UVM testbench parsing tool improving onboarding speed.Project 2: Low-Power IO Sub-System Verification (UART, SPI, Bridges)• Owned TB updates, test creation, and coverage closure.• Enabled subsystem-wide register-validation flow.• Developed regression, coverage, and debug automation frameworks.• Delivered subsystem for 4 SoC programs.• Introduced Jasper connectivity flow adopted by peer teams.Project 3: UFS 3.0 Post-Silicon Debug Support• Supported platform debug for two SoCs.• Enhanced testbench and authored tests for coverage closure

Education

• Hyderabad Instit of Technology and Mangement

  B.Tech, Electronics and Communications Engineering

  2006 — 2010

Skills

• Digital Design
• Xilinx
• Systemverilog
• Modelsim
• C
• Verilog
• C++
• Python
• Ufs
• Functional Verification
• Systemc
• Fpga
• Asic
• Rtl Design
• Uvm
• Formal Verification
• High Level Synthesis
• Pcie
• Integrated Circuit Design
• System Verilog
• Dft
• Mipi Dsi
• Vlsi
• Ncsim
• Jtag
• Upf