Karthigan Suvendran
Digital Asic Design & Verification Engineer @Teledyne E2v
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WORK HISTORY
Digital Asic Design & Verification Engineer @Teledyne E2v
Saint-Égrève, FR
Design and integration of high-speed digital systems (ADC 10-bit 12.8 GSps / DAC 8-bit & 12-bit 12 GSps) with radiation tolerance :• RTL implementation and integration (VHDL/SystemVerilog)• Gate-level simulation with timing annotation• Constraint writing and block synthesis • Development of automated test environments (Python) • Verification, debugging, and performance optimization • Technical documentation and design reports • Support for PnR (Place and Route)
EDUCATION
Lycée Condorcet
Technical Baccalaureate STI (Industrial Sciences and Technologies)
Pierre and Marie Curie University
Master’s degree in Computer Science (Electronic Systems and Computer Systems)
Pierre and Marie Curie University
Bachelor’s degree in EEA (Eletronics, Electrical, Automatic)
Lycée Le Corbusier
CPGE (preparatory classes for grandes écoles) TSI (Technology and industrial sciences)
ABOUT KARTHIGAN SUVENDRAN
Very interested in embedded electronic systems, my ambition is to specialize in this field since my youngest age. That\'s why I built my academic and professional background to acquire scientific and technical skills in this field. Thanks to my studies and my previous experiences, I was able to acquire skills in electronics (FPGA and analog circuit design) and in computer science (C / C ++ programming).
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