Karthick N
Senior Principal Design Engineer at Cadence Design Systems
- Role
- Senior Principal Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Karthick N
SKILLS:• 15 years and 6 months of total experience in ASIC verification.• Verification environment architecture, test plan and verification environment development for block level and subsystem level.• Hands on experience in HVL and Verification methodologies.• Verification HVL: System Verilog.• Methodologies: OVM, UVM.• Tools Used: Cadence IUS, Synopsys VCS, Modelsim, Questasim, IFV.• Experience in Coverage-Driven, Constrained-Random and assertion based verification.• Protocols: LPDDR6, LPDDR55/5X, LPDDR4/4x, DDR4, DDR3, AXI, APB, JTAG, DFI.• Hands on experience in Coverage Analysis using IMC, ICCR.• Version Control: CVS, SVN, GIT.
Experience
Senior Principal Engineer
Jul 2024 — Present · Bengaluru, IN
LPDDR subsystem verification
Education
RV VLSI Design Center
Diploma, ASIC Design
2008 — 2009
Saranathan College Of Engineering
B.E., Electronics & Communication
2004 — 2008
Skills
- Vlsi
- Ovm
- Open Verification Methodology
- Operating Systems
- Perl
- Xilinx
- Systemverilog
- Verilog
- Linux
- Functional Verification
- Asic
- Simulations
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