Kartheesan K

Physical Design Intern @Tata Consultancy Services

Executed RTL-to-GDSII physical design flow for PicoRV32 using Cadence Genus (synthesis) and Cadence Innovus (implementation), achieving successful streamout with full design closure.Designed and analyzed multiple floorplans (L, T,+, square, rectangular) with ~65–80% utilization, improving area efficiency and congestion control.Optimized placement, CTS, and routing, achieving ~10–15% reduction in wirelength/congestion, clock skew 95% routing completion with minimal DRC violations