Karthik Reddy Kistipati

About Karthik Reddy Kistipati

Technical Expertise:1. DFT Planning & Execution - Tile based, Flat & Hierarchical testing of SoCs. Expertise in different compression methods - XOR & MISR. Test timing constraints review & failure analysis. Verification - DRC, LEC & Simulations (Zero-delay & SDF annotated). Standards for test - 1149.1, 1149.6 & 16876. Post-Silicon pattern bring-up & Diagnosis.7. Advanced fault models - Bridging, Cell aware & Small delay. Tool Expertise:1. Cadence: Genus, Modus, Xcelium, Conformal2. Mentor: Tessent SSN, TestKompress, Questa3. Synopsys: Design Compiler, VCS, Verdi Leadership: 1. Mentored & Lead group of Engineers in complex ASIC Designs.2. Team player & collaboration across-Geographies. Conferences: Active participation/ submission of work in International conferences like ITC, VLSID. Invention Disclosures: 1. Low power DFT techniques2. Auto Identification of test points from functional path3. Adaptive Clock Gating for memories with BIST4. Memory BIST through functional interface of memory5. Novel method to Test Resistant Untestable faults during pattern generation

Experience

1. R & d Ic Design Engineer

   Broadcom

   Sep 2023 — Present

Education

• ACE Engineering College, Hyderabad

  Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering

  2008 — 2012

• B. M. S. College of Engineering

  Master of Technology (M.Tech.), Electronics(VLSI Design)

  2013 — 2015

Skills

• Digital Electronics
• C
• Cadence Virtuoso
• Digital Circuit Design
• Microprocessors
• Microsoft Office
• Vlsi
• Etas Inca
• Matlab
• Microelectronics
• Very-Large-Scale Integration (Vlsi)
• Simulink
• Power Electronics
• Xilinx Ise
• Clearcase
• Analog Circuit
• Software Development
• Embedded Systems
• Modelsim
• Electronics
• Cadence
• Pspice
• Electrical Design