Tushar Karan
Senior RTL Design Engineer @Texas Instruments | BITS Pilani
- Role
- Senior Rtl Design Engineer at Texas Instruments
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Tushar Karan
Currently working at Texas Instruments India as a System-on-Chip (SoC) Design Engineer in the Sitara MPU team. I’m part of the RTL Design team, contributing to the development and integration of advanced ARM core-based Microprocessing Units for industrial and embedded applications based out of 16FFC TSMC TechNode.Focused on RTL design, subsystem integration, and performance optimization, I work on state-of-the-art SoC architectures that drive next-generation computing platforms for MPU market.I am a results-driven professional with a strong academic foundation in Electrical Engineering, holding a Bachelor of Technology degree from IEM Kolkata (2019) and a Master of Engineering in Microelectronics from BITS Pilani (2023).During my tenure as an Executive Engineer (Electrical) in the Operations and Maintenance department at Mahanagar Gas Limited, Mumbai (Under GAIL (I) Limited), I had the privilege of overseeing CNG operations in the Raigad and Navi Mumbai regions. This experience allowed me to develop expertise in managing critical electrical systems and ensuring seamless operations in the energy sector.My academic and professional journey has equipped me with a diverse skill set that combines engineering excellence with a deep understanding of microelectronics. I am passionate about leveraging technology to drive innovation and efficiency in the ever-evolving field of electrical engineering.
Experience
Senior Rtl Design Engineer
Feb 2025 — Present · Bengaluru, IN
Working on next-generation TI Sitara Processors for the general purpose market, focusing on- ARM M-Core Sub-System RTL development and TI wrapper infrastructure integration- Integration of Debug, DFT, Clocking and Reset components- Ownership of RTL generation flow and quality checks- Sub-Chip and Top-level SoC integration, including Clocks, Resets, and Debug- Ensuring functional correctness and quality through rigorous RTL quality checks and sign-off.
Education
Birla Institute of Technology and Science, Pilani
Master of Engineering - Microelectronics
Institute Of Engineering and Management
Bachelor of Technology - Electrical Engineering
Jawahar Vidya Mandir, Ranchi.
10th
2001 — 2013
Jawahar Vidya Mandir, Ranchi.
12th, Science
2013 — 2015
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