Karan Shah

About Karan Shah

Working on ASIC/FPGA/SOC Based Network Interface Card.• 5+ Years of Experience in Frontend VLSI Design covering ASIC/FPGA/SOC RTL Design, Integration and Verification.• Proficient across the complete RTL handoff flow—Lint, Synthesis, Timing Analysis, DFT-DRC, CDC, Functional Coverage, and Code Coverage.• Experience of working on Industry standard protocol like AXI4, AXI4-Lite, AXI4-Stream, AXI3 and APB3.• Exposure to Pre and Post Silicon Validation.• Exposure to Scripting Language like TCL, Shell, Perl and Python.• RTL Design of many IPs like AXIS Based Ethernet Frame Generator and Checker, Hubs, Pacer and Bus Converters.Passionate about building reliable, scalable digital systems and contributing to high-impact silicon solutions.

Experience

1. Sr Silicon Design Engineer

   AMD

   Dec 2022 — Present · New Delhi, IN

Education

• Nirma University

  Bachelor of Technology - BTech, Electronics and Communications Engineering

  2016 — 2020