Karan Gupta

About Karan Gupta

With over four years of experience in system-on-chip design and engineering, I am passionate about creating innovative and efficient solutions for complex and challenging problems. My core competencies include RTL coding, lint, CDC, micro-architecture design, and debug fabric implementation. I have a master\'s degree in power systems from the Indian Institute of Technology, Delhi, and I am currently working as a system-on-chip logic design engineer at Intel Corporation, where I collaborate with diverse and talented teams across various product groups and geographies.In my current role, I am responsible for designing and integrating a critical subsystem for PSG group of Intel. I define the micro-architectural implementation spec for the subsystem and implement the same using Verilog. Prior to this I worked with DFD (Design for Debug) team for server, entry client, IoT, and modem products, using both Intel and ARM.I also developed parameterized RTL and glue logic for better post-silicon debug, and coordinate with system architects and front-end and back-end design teams on floorplan, timing, and bounds. I have successfully delivered multiple DFD components for different products, and contributed to the improvement of debug efficiency and quality.

Experience

1. Senior Soc Rtl Design Engineer

   Qualcomm

   Jul 2024 — Present · Bengaluru, IN

   Integrated multiple IPs at the SoC level, ensuring seamless connectivity and functionality. • Developed sensor specifications and topologies aligned with floorplan, meeting physical design and static timing analysis requirements. • Pipeline instantiation based on feedback from STA and PD to facilitate early timing closure.

Education

• Delhi Technological University (Formerly DCE)

  Bachelor of Technology - BTech, Electrical and Electronics Engineering

  2013 — 2017

• Indian Institute of Technology, Delhi

  M.Tech, Power Systems

  2018 — 2020