Karan Tiwari
SMTS @Siemens | Design Verification Intern @Cadence | GET @VodafonIdea Ltd.
- Role
- Senior Member of Technical Staff at Siemens Digital Industries Software
- Location
- Kanpur, UP, IN
- LinkedIn followers
- 500 followers
About Karan Tiwari
Passionate about learning the complex & at the same time interesting concepts lying behind the manufacturing of a semiconductor device in VLSI industry.Currently positioned as a Design Verification Intern @ Cadence Design Systems.Proficient in: UCIe IP Feature Verification Verilog delivery Testbenches DUT-VIP, DUT- DUT UVM Testbenches Functional & Code Coverage Analysis Register Verification. Creating BFMs, Sequences & Testcases. Scripting AMBA APB,AHB,AXIGlimpse of my Technical Skills: Digital Designing Verilog System Verilog OOPs SVA UVM Pearl Linux
Experience
Senior Member of Technical Staff
Siemens Digital Industries Software
Dec 2024 — Present · Noida, IN
Education
Chhatrapati Shahu Ji Maharaj University
Bachelor of Technology
Army Public School (APS)
Intermediate
2017 — 2018
Army Public School (APS)
Highschool
2015 — 2016
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