Karan Koti

About Karan Koti

Involved in the Mobile/Server Processor Physical Design with academic background on entire design cycle of ASICS/processors.• 13+ years of experience doing Physical Design of High Frequency & Low Power Flat/Block level designs in 3nm - 90nm technologies.• 10+ years of Custom CPU Physical Design experience for Mobile/Server products• Experience handling designs (>3M gates) through RTL-GDS2 flow & accommodating pre/post mask ECOs with aggressive project schedules• Quick learner with strong problem-solving abilities, leadership skills, self-motivated, open to adapting new tools/methodologies and mentoring team members• Scripting: TCL/SKILL/PERL/PYTHON• EDA Tools: Fusion Compiler/Primetime/ICV/Formality, Cadence Virtuoso/Innovus, Mentor Graphics Calibre• Flow: Floorplanning, Synthesis, Placement, Clock Tree Synthesis, Routing, Timing Analysis/Fixing, Pre/Post Mask (freeze silicon) ECO, EM/IR fixes, Physical Verification• Member of Physical Design Technical Program Committee for DAC 2018- Present

Experience

1. Principal Engineer

   Arm

   May 2025 — Present · Durham, NC, US

   CPU Physical Design

Education

• Visvesvaraya Technological University

  B.E, Electronics and Communication

  2003 — 2007

• North Carolina State University

  MS, Computer Engineering (Comp Arch & VLSI Systems)

  2010 — 2011

Skills

• Architectural Modeling
• Vhdl
• Soc
• Lvs
• Verilog
• Functional Verification
• Routing
• Spice
• Integrated Circuit Design
• Microprocessors
• Timing
• Java
• Microarchitecture
• Processors
• Clock Tree Synthesis
• Cmos
• Static/Statistical Timing Analysis
• Logic Design
• Circuit Design
• Power Planning
• Perl
• Eda
• Physical Design
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Basic Skill
• Primetime
• Tcl
• Systemverilog
• Power Analysis
• Static Timing Analysis
• Io Planning
• Rtl Design
• Arm
• Python
• C++
• Signal Integrity
• Cadence Virtuoso
• Floorplanning
• Digital Design