Kapil Nagarsenker
Principal Design Engineer at Infineon Technologies Semicondutor India
- Role
- Principal Design Engineer at Infineon Technologies India Pvt Ltd at Infineon Technologies
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Principal Design Engineer at Infineon Technologies India Pvt Ltd
Aug 2012 — Present · IN
Education
Goa University
B.E
1999 — 2003
Center For Development Of Advanced Computing(CDAC)
Certificate Course
2004 — 2004
Birla Institute of Technology and Science, Pilani
Master of Technology (MTech)
2014 — 2016
Skills
- Eda
- Integrated Circuit Design
- Analog Layout
- Ic Layout
- Analog Circuit Design
- Physical Verification
- Cmos
- Vlsi
- Drc
- Mixed Signal
- Circuit Design
- Physical Design
- Sram
- Cadence Virtuoso
- Tcl
- Analog
- Usb
- Asic
- Pll
- Low-Power Design
- Lvs
- Cadence
- Ic
- Soc
- Mixed-Signal Ic Design
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