Kanti Lyles

Experience

1. Principal Engineer

   Condor Computing Corporation

   Sep 2023 — Present · Austin, TX, US

   Responsible for RISC-V CPU frontend branch prediction unit design, emphasizing on microarchitecture and RTL design for high performance superscalar CPU. Collaborated with architects and performance modeling team by engaging in discussions about performance features trade-off considering complexities and gains within a given timeline. Design implementation considering area, power, performance, and timing constraints, within set project timeframe. Conducted formal debug using Jasper and simulations debug using Verisium to improve functionality and processor performance. Produced interface documentation for the block verification partners and for fellow designers interfacing with the frontend.Wrote System Verilog and OVL assertions for identifying issues accurately and timely as they occur. Added debug print statements to enhance availability of relevant information in the simulation log file.

Education

• The University of Texas at Austin

  Electrical Engineering

  1989 — 1993

Skills

• Eda
• Semiconductors
• Microprocessors
• Logic Design
• Rtl Design
• Static Timing Analysis
• Functional Verification
• Powerpc
• Vlsi
• Low-Power Design
• Verilog
• Timing Closure
• Physical Design
• Processors
• Soc
• Asic
• Systemverilog