Kanike P S
Senior ASIC Design Verification Engineer at Texas Instruments
- Role
- Senior Asic Design Verification Engineer at Texas Instruments
- Location
- Madikeri, KA, IN
- LinkedIn followers
- 500 followers
About Kanike P S
Experienced Design Verification Engineer with a demonstrated history of working in the Electrical & Electronic Manufacturing industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Verilog design,Digital Circuits design and Perl Scripting. Strong engineering professional graduated from VTU. Being a Design Verification Engineer,I have worked on test case writing,creating verification environment for test benches in SystemVerilog and UVM environment. I have also worked on creating a I2C Slave BFM in UVM environment. I also have knowledge on PERL scripting. I have also worked on automation and scripting. I also have knowledge on Serial protocols like UART, I2C,SPI and parallel protocol like AXI4 and also Avalon Interface and MDIO
Experience
Senior Asic Design Verification Engineer
Jan 2023 — Present · Bengaluru, IN
Education
Visvesvaraya Technological University
Bachelor of Engineering (B.E.)
2013 — 2017
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