Kanagaraj N

About Kanagaraj N

A Passionate, highly accomplished Hardware engineer with 10 Years of experience from Qualcomm. Have 5+ years of experience as a RTL Design Engineer of next generation IP subsystems of DDRPHY RTL Design. I\'ve extensively worked on integration IP/sub-block designs into IP subsystems, scalable IP designs & micro architecture of sub-blocks in IP design & have experience in low power features/flows. Experienced in characterization of various IO pads ( CUSTOM/GPIO/DDR/LPDDR4 pads) includes timing, power, and noise. Sound Knowledge of writing HDL models ( Frond end model) for all types of IO’s and functional/spice verification of same with respect to schematic and HDL. Lead for Analog model creation,Tetra max validation of the same and characterization of all DDR/LPDDR interfaces. Earlier experience in ASIC Standard cells Design, Layout and characterization for various nodes and technologies. Earlier experience in Physical design flow qualification of standard cell libraries and Backend tools for the same.

Experience

1. Senior Staff Engineer

   Qualcomm

   Nov 2022 — Present

Education

• Anna University Chennai

  ME, Applied Electronics

  2003 — 2005

Skills

• Testing
• Verilog
• Vlsi
• Debugging
• Asic
• Modelsim
• Soc
• Analog
• Semiconductors
• Functional Verification
• Integrated Circuit Design
• Ic
• Primetime
• Perl
• Eda
• Cmos
• Physical Design
• Cadence Virtuoso
• Timing Closure