Kamlesh Pillai

About Kamlesh Pillai

Over 10 years of experience in research and development of accelerator, microarchitecture definition, frontend design, physical design, IP development. Expert in designing energy efficient, configurable, and scalable accelerators for Deep learning, In-memory/Near memory compute and GPUs.Worked closely with architects on various problems and defined efficient microarchitecture, designed, and productized domain specific accelerators for 3D rendering pipe of GPU across multiplegenerations (5+ tape out). Developed, patented (40+granted/submitted), and published (8+) novel in-memory compute methods to accelerate AI workloads, hardware accelerators for multi-dimension convolution operation and similar hardware-software co-designed solutions. Developed leadership skills – by guiding and working with interns and college graduates in small teams over years across geo and mentored them.Strong experience in hardwired accelerator architecture, data/control flow optimization, area and power optimized implementation, high Level Modelling for accelerators, low area & low power micro-architecture/RTL design (in SystemVerilog using VCS-DVE), logic synthesis (Design Compiler), place and route (ICC/ICC-II), timing (PTPX) and DRC Closure, IP development for ASIC.Hold a master’s Degree in Electronics and Communication with specialization in Electronics and Communication from Dept. of Electronics and Communication, Nirma University, Gujarat, India.Research and development interests are towards finding novel methods for low power, highly efficient and configurable accelerator for AI workloads.

Experience

1. Asic Design Engineer

   Meta

   Dec 2024 — Present

Education

• Nirma University

  Master of Technology (M.Tech.), Electrical, Electronics and Communications Engineering

  2013 — 2015