Kameshwar Kaushik Chavali
- Role
- Asic Design Engineer at Apple
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Kameshwar Kaushik Chavali
Experienced in - ASIC/Design: Verilog, SystemVerilog, Reuse Methodology, SVA…
Experience
Asic Design Engineer
Jun 2019 — Present
Skills
- Static Timing Analysis
- Verilog
- Logic Analyzer
- Network Processors
- Tcl
- Kicad
- Modelsim
- Fpga
- Functional Verification
- Computer Architecture
- Hardware Architecture
- Tcp/Ip
- Beekeeping
- I2c
- Vlsi
- Vhdl
- Ethernet
- Reinforcement Learning
- Embedded Systems
- Asic
- Ip Networking
- Ios Development
- Systemverilog
- Pcb Design
- Ultra Low Latency
- Xilinx
- Rtl Coding
- Microprocessors
- Arm
- Integrated Circuit Design
- Electronics Hardware Design
- Cadence Virtuoso
- Markov Decision Processes
- Timing Closure
- Soc
- Pcie
- Low-Power Design
- Uvm
- Oop
- Debugging
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