Kamesh Malla

About Kamesh Malla

Over 23 years of Professional Experience in Physical Design & Circuit Design Space Involved in various technology node Tape-outs (7nm,16nm,28nm, 40nm, 65nm and 90nm)Physical Design using RTL to GDS Implementation FlowsWorked on high-speed Mesh/Interconnect SOC clusters in 16nmWorked on full chip integration for a 20-CPU MIPS SOC in 28nmExpertise with Custom Data Path and Mega Cells Composition Low Power methodology for Microprocessor DesignProficient in all aspects of Digital Circuit Design using CMOS technology, Layout DesignHands on exposure in working with Verilog, Test Bench Writing, VCS Logic Simulations Well-versed in TCL/Shell/Perl CodingExcellent communication, Problem Solving, Analytical and Time Management SkillsSKILLS Place & Route: Cadence Innvous, Atoptech Aprisa Synthesis Tools: Synopsys DC STA Tools: Cadence Tempus/ Synopsys Prime Time Physical Verification Tools: Mentor Graphics Calibre, Cadence PVS Custom Circuit Tools: Cadence Virtuoso/Schematic Entry Tools TCL, Bash Shell scripting Verilog Coding, VCS Simulations Spice Simulations

Experience

1. Principal Engineer Manager

   Cisco

   Feb 2026 — Present

Education

• The University of Toledo

  MS, Electrical Engineering

  2000 — 2002

• GITAM University

  BS, Electronics and Instrumentation

  1995 — 1999