Kalyana Chakravarthy

Experience

1. Engineering Manager - Physical Design

   Synopsys Inc

   Oct 2018 — Present · Hyderabad, IN

   Driving IP and Chip level projects right from RTL Synthesis(including DFT scan insertion) to PnR/EMIR/STA/Formality/VCLP/PV and also Package & Foundry activities which are of High Frequency and Low Power designs and based on Lower technology nodes i.e 5nm, 7nm, 12nm, 16nm. Have solid track record of taping out IPs and Chips in 5nm and above for Automotive and Consumer Grades. Thourough technical understanding of Backend challenges such as Place and route on advanced process nodes, Static Timing Analysis for High frequency designs, Formal Verification, Low Power Verification etc. Solid understanding of overall chip design cycle including Frontend design, DFT, GLS, Analog/Mixed-Signal design. Leading a team of 15 to 20 Engineers which includes striving diligently in getting feedback on day to day activities of project from each stakeholder, Ensuring quality and collaboration with dedication and fun, cutting through clutter & noise in brainstorming sessions to bring forward solution for problem, technical acumen of getting the things straight and organize priorities for achieving optimized solutions, providing status updates to Top Management and able to manage ambiguity and schedule challenges

Education

• Visvesvaraya Technological University

  M.Tech, VLSI

  2004 — 2006

• Visvesvaraya Technological University

  B.Tech, ECE

  1998 — 2003